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an important notice at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. production data. sn74aup1g17 sces579j ? june 2004 ? revised september 2017 sn74aup1g17 low-power single schmitt-trigger buffer 1 1 features 1 ? latch-up performance exceeds 100 ma per jesd 78, class ii ? esd performance tested per jesd 22 ? 2000-v human-body model (a114-b, class ii) ? 1000-v charged-device model (c101) ? available in the texas instruments nanostar ? package ? low static-power consumption (i cc = 0.9 a maximum) ? low dynamic-power consumption (c pd = 4.4 pf typical at 3.3 v) ? low input capacitance (c i = 1.5 pf typical) ? low noise ? overshoot and undershoot < 10% of v cc ? i off supports partial-power-down mode operation ? includes schmitt-trigger inputs ? wide operating v cc range of 0.8 v to 3.6 v ? optimized for 3.3-v operation ? 3.6-v i/o tolerant to support mixed-mode signal operation ? t pd = 5.1 ns maximum at 3.3 v ? suitable for point-to-point applications 2 applications ? grid infrastructure ? pc & notebooks ? tablets ? factory automation & control ? gaming ? server 3 description the aup family of devices is ti ' s premier solution to the industry ' s low-power needs in battery-powered portable applications. this family ensures a very low static- and dynamic-power consumption across the entire v cc range of 0.8 v to 3.6 v, resulting in increased battery life. this product also maintains excellent signal integrity (see aup ? the lowest- power family and excellent signal integrity ). this device functions as an independent gate with schmitt-trigger inputs, which allows for slow input transition and better switching-noise immunity at the input. nanostar ? package technology is a major breakthrough in ic packaging concepts, using the die as the package. this device is fully specified for partial-power-down applications using i off . the i off circuitry disables the outputs when the device is powered down. this inhibits current backflow into the device which prevents damage to the device. device information (1) part number package body size (nom) sn74aup1g17dbv sot-23 (5) 1.60 mm 2.90 mm sn74aup1g17dck sc70 (5) 1.25 mm 2.00 mm sn74aup1g17drl sot-5x3 (5) 1.60 mm 1.20 mm sn74aup1g17dry son (6) 1.00 mm 1.45 mm sn74aup1g17dsf son (6) 1.00 mm 1.00 mm sn74aup1g17yfp dsbga (4) 0.76 mm 0.76 mm SN74AUP1G17YZP dsbga (5) 0.89 mm 1.39 mm sn74aup1g17dpw x2son (5) 0.80 mm 0.80 mm (1) for all available packages, see the orderable addendum at the end of the data sheet. logic diagram (positive logic) (dbv, dck, dpw, drl, drt, dry, and yzp packages) logic diagram (positive logic) (yfp package) a y 1 3 a y 2 4 tools & software technical documents ordernow productfolder support &community
2 sn74aup1g17 sces579j ? june 2004 ? revised september 2017 www.ti.com product folder links: sn74aup1g17 submit documentation feedback copyright ? 2004 ? 2017, texas instruments incorporated table of contents 1 features .................................................................. 1 2 applications ........................................................... 1 3 description ............................................................. 1 4 revision history ..................................................... 2 5 pin configuration and functions ......................... 3 6 specifications ......................................................... 4 6.1 absolute maximum ratings ...................................... 4 6.2 esd ratings .............................................................. 4 6.3 recommended operating conditions ....................... 4 6.4 thermal information .................................................. 5 6.5 electrical characteristics ........................................... 5 6.6 switching characteristics: c l = 5 pf ........................ 7 6.7 switching characteristics: c l = 10 pf ...................... 8 6.8 switching characteristics: c l = 15 pf ...................... 8 6.9 switching characteristics: c l = 30 pf ...................... 9 6.10 operating characteristics ........................................ 9 6.11 typical characteristics ............................................ 9 7 parameter measurement information ................ 10 7.1 propagation delays, setup and hold times, and pulse duration ......................................................... 10 7.2 enable and disable times ...................................... 11 8 detailed description ............................................ 12 8.1 overview ................................................................. 12 8.2 functional block diagrams ..................................... 12 8.3 feature description ................................................. 12 8.4 device functional modes ........................................ 13 9 application and implementation ........................ 14 9.1 application information ............................................ 14 9.2 typical application .................................................. 14 10 power supply recommendations ..................... 16 11 layout ................................................................... 16 11.1 layout guidelines ................................................. 16 11.2 layout example .................................................... 16 12 device and documentation support ................. 17 12.1 documentation support ........................................ 17 12.2 receiving notification of documentation updates 17 12.3 community resources .......................................... 17 12.4 trademarks ........................................................... 17 12.5 electrostatic discharge caution ............................ 17 12.6 glossary ................................................................ 17 13 mechanical, packaging, and orderable information ........................................................... 17 4 revision history note: page numbers for previous revisions may differ from page numbers in the current version. changes from revision i (march 2010) to revision j page ? added applications , device information table, pin configuration and functions section, esd ratings table, thermal information table, feature description section, application and implementation section, power supply recommendations section, layout section, device and documentation support section, and mechanical, packaging, and orderable information section ...................................................................................................................... 1 ? deleted ordering information table, see mechanical, packaging, and orderable information at the end of the data sheet ...................................................................................................................................................................................... 1
3 sn74aup1g17 www.ti.com sces579j ? june 2004 ? revised september 2017 product folder links: sn74aup1g17 submit documentation feedback copyright ? 2004 ? 2017, texas instruments incorporated 5 pin configuration and functions dbv package 5-pin sot-23 top view n.c. ? no internal connection. dck package 5-pin sc70 top view drl package 5-pin sot-5x3 top view dpw package 5-pin x2son top view dry package 6-pin son top view dsf package 6-pin son top view yfp package 4-pin dsbga bottom view see mechanical drawings for dimensions. yzp package 5-pin dsbga bottom view dnu ? do not use pin functions pin i/o description name dbv, dck, drl, dpw dry, dsf yfp yzp a 2 2 a1 b1 i input dnu ? ? ? a1 ? do not use gnd 3 3 b1 c1 ? ground n.c. 1 1 ? ? ? no connection 5 v cc 5 6 a2 a2 ? positive supply y 4 4 b2 c2 o output 3 2 4 5 1 n.c. v cc y a gnd y v cc a nc gnd 3 2 4 5 1 n.c. v cc y a gnd gnd a n.c. n.c. 6 5 4 2 3 y v cc 1 3 2 4 5 1 n.c. v cc y a gnd 1 2 c b a not to scale gnd y a dnu v cc gnd y 3 4 a 2 5 n.c. 6 1 n.c. v cc 1 2 b a not to scale gnd y a v cc
4 sn74aup1g17 sces579j ? june 2004 ? revised september 2017 www.ti.com product folder links: sn74aup1g17 submit documentation feedback copyright ? 2004 ? 2017, texas instruments incorporated (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions . exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) the input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. 6 specifications 6.1 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) (1) min max unit v cc supply voltage ? 0.5 4.6 v v i input voltage (2) ? 0.5 4.6 v v o voltage range applied to any output in the high-impedance or power-off state (2) ? 0.5 4.6 v v o output voltage range in the high or low state (2) ? 0.5 v cc + 0.5 v i ik input clamp current v i < 0 ? 50 ma i ok output clamp current v o < 0 ? 50 ma i o continuous output current 20 ma continuous current through v cc or gnd 50 ma t j junction temperature 150 c t stg storage temperature ? 65 150 c (1) jedec document jep155 states that 500-v hbm allows safe manufacturing with a standard esd control process. (2) jedec document jep157 states that 250-v cdm allows safe manufacturing with a standard esd control process. 6.2 esd ratings value unit v (esd) electrostatic discharge human-body model (hbm), per ansi/esda/jedec js-001 (1) 2000 v charged-device model (cdm), per jedec specification jesd22-c101 (2) 1000 (1) all unused inputs of the device must be held at v cc or gnd to ensure proper device operation. see implications of slow or floating cmos inputs . (2) defined by the signal-integrity requirements and design-goal priorities 6.3 recommended operating conditions see (1) min max unit v cc supply voltage 0.8 3.6 v v i input voltage 0 3.6 v v o output voltage 0 v cc v i oh (2) high-level output current v cc = 0.8 v ? 20 a v cc = 1.1 v ? 1.1 ma v cc = 1.4 v ? 1.7 v cc = 1.65 ? 1.9 v cc = 2.3 v ? 3.1 v cc = 3 v ? 4 i ol (2) low-level output current v cc = 0.8 v 20 a v cc = 1.1 v 1.1 ma v cc = 1.4 v 1.7 v cc = 1.65 v 1.9 v cc = 2.3 v 3.1 v cc = 3 v 4 t a operating free-air temperature ? 40 85 c
5 sn74aup1g17 www.ti.com sces579j ? june 2004 ? revised september 2017 product folder links: sn74aup1g17 submit documentation feedback copyright ? 2004 ? 2017, texas instruments incorporated (1) for more information about traditional and new thermal metrics, see the semiconductor and ic package thermal metrics application report. 6.4 thermal information thermal metric (1) sn74aup1g17 unit dbv (sot-23) dck (sc70) drl (sot-5x3) dpw (x2son) dry (son) dsf (son) yfp (dsbga) yzp (dsbga) 5 pins 5 pins 5 pins 5 pins 6 pins 6 pins 4 pins 5 pins r ja junction-to-ambient thermal resistance 267.2 284.1 294.7 489.2 347.8 386.2 179.3 146.2 c/w r jc(top) junction-to-case (top) thermal resistance 191.9 208.5 132.5 226.3 237.7 192.9 2.8 1.4 c/w r jb junction-to-board thermal resistance 101.1 103.1 143.6 352.9 210.6 242.2 58.3 39.3 c/w jt junction-to-top characterization parameter 83.0 76.6 14.5 38.2 64.4 28.9 1.1 0.7 c/w jb junction-to-board characterization parameter 100.8 102.3 144.1 352.1 210.6 241.9 58.6 39.8 c/w r jc(bot) junction-to-case (bottom) thermal resistance n/a n/a n/a 150.8 n/a n/a n/a n/a c/w 6.5 electrical characteristics over operating free-air temperature range (unless otherwise noted) parameter test conditions v cc min typ max unit v t+ positive-going input threshold voltage t a = 25 c 0.8 v 0.3 0.6 v t a = ? 40 c to +85 c 0.3 0.6 t a = 25 c 1.1 v 0.53 0.9 t a = ? 40 c to +85 c 0.53 0.9 t a = 25 c 1.4 v 0.74 1.11 t a = ? 40 c to +85 c 0.74 1.11 t a = 25 c 1.65 v 0.91 1.29 t a = ? 40 c to +85 c 0.91 1.29 t a = 25 c 2.3 v 1.37 1.77 t a = ? 40 c to +85 c 1.37 1.77 t a = 25 c 3 v 1.88 2.29 t a = ? 40 c to +85 c 1.88 2.29 v t ? negative-going input threshold voltage t a = 25 c 0.8 v 0.1 0.6 v t a = ? 40 c to +85 c 0.1 0.6 t a = 25 c 1.1 v 0.26 0.65 t a = ? 40 c to +85 c 0.26 0.65 t a = 25 c 1.4 v 0.39 0.75 t a = ? 40 c to +85 c 0.39 0.75 t a = 25 c 1.65 v 0.47 0.84 t a = ? 40 c to +85 c 0.47 0.84 t a = 25 c 2.3 v 0.69 1.04 t a = ? 40 c to +85 c 0.69 1.04 t a = 25 c 3 v 0.88 1.24 t a = ? 40 c to +85 c 0.88 1.24
6 sn74aup1g17 sces579j ? june 2004 ? revised september 2017 www.ti.com product folder links: sn74aup1g17 submit documentation feedback copyright ? 2004 ? 2017, texas instruments incorporated electrical characteristics (continued) over operating free-air temperature range (unless otherwise noted) parameter test conditions v cc min typ max unit v t hysteresis (v t+ ? v t ? ) t a = 25 c 0.8 v 0.07 0.5 v t a = ? 40 c to +85 c 0.07 0.5 t a = 25 c 1.1 v 0.08 0.46 t a = ? 40 c to +85 c 0.08 0.46 t a = 25 c 1.4 v 0.18 0.56 t a = ? 40 c to +85 c 0.18 0.56 t a = 25 c 1.65 v 0.27 0.66 t a = ? 40 c to +85 c 0.27 0.66 t a = 25 c 2.3 v 0.53 0.92 t a = ? 40 c to +85 c 0.53 0.92 t a = 25 c 3 v 0.79 1.31 t a = ? 40 c to +85 c 0.79 1.31 v oh i oh = ? 20 a t a = 25 c 0.8 v to 3.6 v v cc ? 0.1 v t a = ? 40 c to +85 c v cc ? 0.1 i oh = ? 1.1 ma t a = 25 c 1.1 v 0.75 v cc t a = ? 40 c to +85 c 0.7 v cc i oh = ? 1.7 ma t a = 25 c 1.4 v 1.11 t a = ? 40 c to +85 c 1.03 i oh = ? 1.9 ma t a = 25 c 1.65 v 1.32 t a = ? 40 c to +85 c 1.3 i oh = ? 2.3 ma t a = 25 c 2.3 v 2.05 t a = ? 40 c to +85 c 1.97 i oh = ? 3.1 ma t a = 25 c 1.9 t a = ? 40 c to +85 c 1.85 i oh = ? 2.7 ma t a = 25 c 3 v 2.72 t a = ? 40 c to +85 c 2.67 i oh = ? 4 ma t a = 25 c 2.6 t a = ? 40 c to +85 c 2.55 v ol i ol = 20 a t a = 25 c 0.8 v to 3.6 v 0.1 v t a = ? 40 c to +85 c 0.1 i ol = 1.1 ma t a = 25 c 1.1 v 0.3 v cc t a = ? 40 c to +85 c 0.3 v cc i ol = 1.7 ma t a = 25 c 1.4 v 0.31 t a = ? 40 c to +85 c 0.37 i ol = 1.9 ma t a = 25 c 1.65 v 0.31 t a = ? 40 c to +85 c 0.35 i ol = 2.3 ma t a = 25 c 2.3 v 0.31 t a = ? 40 c to +85 c 0.33 i ol = 3.1 ma t a = 25 c 0.44 t a = ? 40 c to +85 c 0.45 i ol = 2.7 ma t a = 25 c 3 v 0.31 t a = ? 40 c to +85 c 0.33 i ol = 4 ma t a = 25 c 0.44 t a = ? 40 c to +85 c 0.45
7 sn74aup1g17 www.ti.com sces579j ? june 2004 ? revised september 2017 product folder links: sn74aup1g17 submit documentation feedback copyright ? 2004 ? 2017, texas instruments incorporated electrical characteristics (continued) over operating free-air temperature range (unless otherwise noted) parameter test conditions v cc min typ max unit i i a inputs v i = gnd to 3.6 v t a = 25 c 0 v to 3.6 v 0.1 a t a = ? 40 c to +85 c 0.5 i off v i or v o = 0 v to 3.6 v t a = 25 c 0 v 0.2 a t a = ? 40 c to +85 c 0.6 i off v i or v o = 0 v to 3.6 v t a = 25 c 0 v to 0.2 v 0.2 a t a = ? 40 c to +85 c 0.6 i cc v i = gnd or (v cc to 3.6 v), i o = 0 t a = 25 c 0.8 v to 3.6 v 0.5 a t a = ? 40 c to +85 c 0.9 i cc v i = v cc 0.6 v, i o = 0 t a = 25 c 3.3 v 40 a t a = ? 40 c to +85 c 50 c i v i = v cc or gnd 0 v 1.5 pf 3.6 v 1.5 c o v o = gnd 0 v 2.5 pf 6.6 switching characteristics: c l = 5 pf over recommended operating free-air temperature range, c l = 5 pf (unless otherwise noted) (see figure 3 and figure 4 ) parameter from (input) to (output) test conditions min typ max unit t pd a y v cc = 0.8 v t a = 25 c 22.7 ns v cc = 1.2 v 0.1 v t a = 25 c 6.3 8 12.8 t a = ? 40 c to +85 c 3.9 14.6 v cc = 1.5 v 0.1 v t a = 25 c 4.6 5.8 8.4 t a = ? 40 c to +85 c 2.8 10 v cc = 1.8 v 0.15 v t a = 25 c 3.9 4.8 7.2 t a = ? 40 c to +85 c 2.4 8.1 v cc = 2.5 v 0.2 v t a = 25 c 3.1 3.6 5.1 t a = ? 40 c to +85 c 2 6.1 v cc = 3.3 v 0.3 v t a = 25 c 2.7 3 4.4 t a = ? 40 c to +85 c 1.9 5.1
8 sn74aup1g17 sces579j ? june 2004 ? revised september 2017 www.ti.com product folder links: sn74aup1g17 submit documentation feedback copyright ? 2004 ? 2017, texas instruments incorporated 6.7 switching characteristics: c l = 10 pf over recommended operating free-air temperature range, c l = 10 pf (unless otherwise noted) (see figure 3 and figure 4 ) parameter from (input) to (output) test conditions min typ max unit t pd a y v cc = 0.8 v t a = 25 c 25.1 ns v cc = 1.2 v 0.1 v t a = 25 c 7.1 9.1 13.8 t a = ? 40 c to +85 c 4.7 15.6 v cc = 1.5 v 0.1 v t a = 25 c 5.2 6.5 9.4 t a = ? 40 c to +85 c 3.4 11 v cc = 1.8 v 0.15 v t a = 25 c 4.5 5.4 8 t a = ? 40 c to +85 c 2.9 9 v cc = 2.5 v 0.2 v t a = 25 c 3.5 4.2 5.7 t a = ? 40 c to +85 c 2.4 6.8 v cc = 3.3 v 0.3 v t a = 25 c 3.1 3.5 4.9 t a = ? 40 c to +85 c 2.2 5.7 6.8 switching characteristics: c l = 15 pf over recommended operating free-air temperature range, c l = 15 pf (unless otherwise noted) (see figure 3 and figure 4 ) parameter from (input) to (output) test conditions min typ max unit t pd a y v cc = 0.8 v t a = 25 c 27.6 ns v cc = 1.2 v 0.1 v t a = 25 c 7.8 10.1 14.8 t a = ? 40 c to +85 c 5.3 16.7 v cc = 1.5 v 0.1 v t a = 25 c 5.8 7.4 10.3 t a = ? 40 c to +85 c 3.9 12 v cc = 1.8 v 0.15 v t a = 25 c 5 6.1 8.8 t a = ? 40 c to +85 c 3.4 10 v cc = 2.5 v 0.2 v t a = 25 c 4 4.7 6.4 t a = ? 40 c to +85 c 2.8 7.5 v cc = 3.3 v 0.3 v t a = 25 c 3.5 4.1 5.4 t a = ? 40 c to +85 c 2.6 6.2
9 sn74aup1g17 www.ti.com sces579j ? june 2004 ? revised september 2017 product folder links: sn74aup1g17 submit documentation feedback copyright ? 2004 ? 2017, texas instruments incorporated 6.9 switching characteristics: c l = 30 pf over recommended operating free-air temperature range, c l = 30 pf (unless otherwise noted) (see figure 3 and figure 4 ) parameter from (input) to (output) test conditions min typ max unit t pd a y v cc = 0.8 v t a = 25 c 35.1 ns v cc = 1.2 v 0.1 v t a = 25 c 10 13.1 18.1 t a = ? 40 c to +85 c 7.5 19.8 v cc = 1.5 v 0.1 v t a = 25 c 7.4 9.6 12.9 t a = ? 40 c to +85 c 5.6 14.9 v cc = 1.8 v 0.15 v t a = 25 c 6.4 7.9 11 t a = ? 40 c to +85 c 4.8 12.4 v cc = 2.5 v 0.2 v t a = 25 c 5.2 6.1 7.9 t a = ? 40 c to +85 c 4 9.3 v cc = 3.3 v 0.3 v t a = 25 c 4.6 5.3 6.7 t a = ? 40 c to +85 c 3.6 7.7 6.10 operating characteristics t a = 25 c parameter test conditions v cc typ unit c pd power dissipation capacitance f = 10 mhz 0.8 v 4 pf 1.2 v 0.1 v 4 1.5 v 0.1 v 4 1.8 v 0.15 v 4 2.5 v 0.2 v 4.2 3.3 v 0.3 v 4.4 6.11 typical characteristics figure 1. aup ? the lowest-power family figure 2. excellent signal integrity ?0.5 0 0.5 1 1.5 2 2.5 3 3.5 0 5 10 15 20 25 30 35 40 45 time ? ns voltage ? v ? aup1g08 data at c l = 15 pf switching characteristics at 25 mhz ? output input aup lvc aup aup lvc static-power consumption ( a) m dynamic-power consumption (pf) ? single, dual, and triple gates 3.3-v logic ? 3.3-v logic ? 0% 20% 40% 60% 80% 100% 0% 20% 40% 60% 80% 100%
10 sn74aup1g17 sces579j ? june 2004 ? revised september 2017 www.ti.com product folder links: sn74aup1g17 submit documentation feedback copyright ? 2004 ? 2017, texas instruments incorporated 7 parameter measurement information 7.1 propagation delays, setup and hold times, and pulse duration figure 3. load circuit and voltage waveforms v m from output under test c l (see note a) load circuit 1 m w voltage waveforms propagation delay times inverting and noninverting outputs t plh t phl t phl t plh v oh v oh v ol v ol v i 0 v input outputoutput notes: a. c l includes probe and jig capacitance. b. all input pulses are supplied by generators having the following chara cteristics: prr 10 mhz, z o = 50 w, t r /t f = 3 ns. c. the outputs are measured one at a time, with one transition per measuremen t. d. t plh and t phl are the same as t pd . e. all parameters and waveforms are not applicable to all devices. v m v m v m v m v m 5, 10, 15, 30 pf v cc /2 v cc v cc = 1.2 v 0.1 v v cc = 0.8 v v cc = 1.5 v 0.1 v v cc = 1.8 v 0.15 v v cc = 2.5 v 0.2 v v cc = 3.3 v 0.3 v 5, 10, 15, 30 pf v cc /2 v cc 5, 10, 15, 30 pf v cc /2 v cc 5, 10, 15, 30 pf v cc /2 v cc c l v m v i 5, 10, 15, 30 pf v cc /2 v cc 5, 10, 15, 30 pf v cc /2 v cc t h t su data input timing input v cc 0 vv cc 0 v 0 v t w input voltage waveforms setup and hold times voltage waveforms pulse duration v cc /2 v cc /2 v cc /2 v cc /2 v cc v cc /2
11 sn74aup1g17 www.ti.com sces579j ? june 2004 ? revised september 2017 product folder links: sn74aup1g17 submit documentation feedback copyright ? 2004 ? 2017, texas instruments incorporated 7.2 enable and disable times figure 4. load circuit and voltage waveforms notes: a. c l includes probe and jig capacitance. b. waveform 1 is for an output with internal conditions such that the output is l ow, except when disabled by the output control. waveform 2 is for an output with internal conditions such that the output is high, exc ept when disabled by the output control. c. all input pulses are supplied by generators having the following chara cteristics: prr 10 mhz, z o = 50 w, t r /t f = 3 ns. d. the outputs are measured one at a time, with one transition per measuremen t. e. t plz and t phz are the same as t dis . f. t pzl and t pzh are the same as t en . g. all parameters and waveforms are not applicable to all devices. 5, 10, 15, 30 pf v cc /2 v cc 0.15 v v cc = 1.2 v 0.1 v v cc = 0.8 v v cc = 1.5 v 0.1 v v cc = 1.8 v 0.15 v v cc = 2.5 v 0.2 v v cc = 3.3 v 0.3 v 5, 10, 15, 30 pf v cc /2 v cc 0.1 v 5, 10, 15, 30 pf v cc /2 v cc 0.1 v 5, 10, 15, 30 pf v cc /2 v cc 0.1 v c l v m v i v d 5, 10, 15, 30 pf v cc /2 v cc 0.15 v 5, 10, 15, 30 pf v cc /2 v cc 0.3 v output waveform 1 s1 at 2 v cc (see note b) output waveform 2 s1 at gnd (see note b) v ol v oh t pzl t pzh t plz t phz v cc 0 v v ol + v d v oh ? v d 0 v v cc voltage waveforms enable and disable times low- and high-level enabling output control v cc /2 v cc /2 v cc /2 v cc /2 t plz /t pzl t phz /t pzh 2 v cc gnd test s1 from output under test c l (see note a) load circuit s1 gnd 5 k w 5 k w 2 v cc
12 sn74aup1g17 sces579j ? june 2004 ? revised september 2017 www.ti.com product folder links: sn74aup1g17 submit documentation feedback copyright ? 2004 ? 2017, texas instruments incorporated 8 detailed description 8.1 overview this device functions as an independent gate with schmitt-trigger inputs, which allows for slow input transition and better switching-noise immunity at the input. the aup family is ti's premier solution to the industry's low power needs in battery-powered portable applications. this family assures a very low static and dynamic power consumption across the entire vcc range of 0.8 v to 3.6 v, resulting in an increased battery life. this device is fully specified for partial-power-down applications using i off . the i off circuitry disables the outputs when the device is powered down. this inhibits current backflow into the device which prevents damage to the device and excess power consumption. 8.2 functional block diagrams figure 5. logic diagram (positive logic) (dbv, dck, dpw, drl, drt, dry, and yzp packages) figure 6. logic diagram (positive logic) (yfp package) 8.3 feature description 8.3.1 balanced high-drive cmos push-pull outputs a balanced output allows the device to sink and source similar currents. the high drive capability of this device creates fast edges into light loads so routing and load conditions should be considered to prevent ringing. additionally, the outputs of this device are capable of driving larger currents than the device can sustain without being damaged. it is important for the power output of the device to be limited to avoid thermal runaway and damage due to over-current. the electrical and thermal limits defined the in the absolute maximum ratings table must be followed at all times. 8.3.2 standard cmos inputs standard cmos inputs are high impedance and are typically modelled as a resistor in parallel with the input capacitance given in the electrical characteristics table. the worst case resistance is calculated with the maximum input voltage, given in the absolute maximum ratings table, and the maximum input leakage current, given in the electrical characteristics table, using ohm's law (r = v i). signals applied to the inputs need to have fast edge rates, as defined by t/ v in recommended operating conditions table to avoid excessive currents and oscillations. if a slow or noisy input signal is required, a device with a schmitt-trigger input should be used to condition the input signal prior to the standard cmos input. a y 1 3 a y 2 4
13 sn74aup1g17 www.ti.com sces579j ? june 2004 ? revised september 2017 product folder links: sn74aup1g17 submit documentation feedback copyright ? 2004 ? 2017, texas instruments incorporated feature description (continued) 8.3.3 clamp diodes the inputs and outputs to this device have negative clamping diodes. caution voltages beyond the values specified in the absolute maximum ratings table can cause damage to the device. the input negative-voltage and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. figure 7. electrical placement of clamping diodes for each input and output 8.3.4 partial power down (i off ) the inputs and outputs for this device enter a high impedance state when the supply voltage is 0 v. the maximum leakage into or out of any input or output pin on the device is specified by i off in the electrical characteristics table. 8.3.5 over-voltage tolerant inputs input signals to this device can be driven above the supply voltage so long as they remain below the maximum input voltage value specified in the absolute maximum ratings table. 8.4 device functional modes table 1 lists the functional modes of the sn74aup1g17 device. table 1. function table input a output y h h l l gnd logic input output v cc device -i ik -i ok
14 sn74aup1g17 sces579j ? june 2004 ? revised september 2017 www.ti.com product folder links: sn74aup1g17 submit documentation feedback copyright ? 2004 ? 2017, texas instruments incorporated 9 application and implementation note information in the following applications sections is not part of the ti component specification, and ti does not warrant its accuracy or completeness. ti ? s customers are responsible for determining suitability of components for their purposes. customers should validate and test their design implementation to confirm system functionality. 9.1 application information there are many situations in which a device needs to be initialized or held off for a short time at system turn-on. this application of the sn74aup1g17 utilizes the delay created in an rc circuit to hold a line low for a short time when the system is first started, then maintains the line high while the system operates. the sn74aup1g17 is ideal for this application because it must be tied directly to the primary supply for correct operation and is designed to draw minimal supply current during operation. 9.2 typical application figure 8. turn-on pulse generator (normally high output) 9.2.1 design requirements this device uses cmos technology and has balanced output drive. take care to avoid bus contention because it can drive currents that would exceed maximum limits. the drive strength also creates fast edges into light loads, so routing and load conditions should be considered to prevent ringing. 9.2.2 detailed design procedure 1. recommended input conditions: ? for specified high and low levels, see (v t+ and v t- ) in the electrical characteristics table. ? inputs are overvoltage tolerant allowing them to go as high as (v i max) in the absolute maximum ratings table at any valid v cc . 2. recommended output conditions: ? load currents should not exceed (i o max) per output and should not exceed (continuous current through v cc or gnd) total current for the part. these limits are located in the absolute maximum ratings table. v cc v o v c
15 sn74aup1g17 www.ti.com sces579j ? june 2004 ? revised september 2017 product folder links: sn74aup1g17 submit documentation feedback copyright ? 2004 ? 2017, texas instruments incorporated typical application (continued) 9.2.3 application curve figure 9. simulated output response to supply turn-on time ( w ) voltage (% of v cc ) 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 0 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% v c v cc v o
16 sn74aup1g17 sces579j ? june 2004 ? revised september 2017 www.ti.com product folder links: sn74aup1g17 submit documentation feedback copyright ? 2004 ? 2017, texas instruments incorporated 10 power supply recommendations the power supply can be any voltage between the min and max supply voltage rating located in the recommended operating conditions table. each v cc pin should have a good bypass capacitor to prevent power disturbance. it is ok to parallel multiple bypass caps to reject different frequencies of noise. 0.1- f and 1- f capacitors are commonly used in parallel. the bypass capacitor must be installed as close to the power pin as possible for best results. 11 layout 11.1 layout guidelines even low data rate digital signals can contain high-frequency signal components due to fast edge rates. when a printed-circuit board (pcb) trace turns a corner at a 90 angle, a reflection can occur. a reflection occurs primarily because of the change of width of the trace. at the apex of the turn, the trace width increases to 1.414 times the width. this increase upsets the transmission-line characteristics, especially the distributed capacitance and self ? inductance of the trace which results in the reflection. not all pcb traces can be straight and therefore some traces must turn corners. figure 10 shows progressively better techniques of rounding corners. only the last example (best) maintains constant trace width and minimizes reflections. an example layout is given in figure 11 for the dpw (x2son-5) package. this example layout includes a 0402 (metric) capacitor and uses the measurements found in the example board layout appended to this end of this datasheet. a via of diameter 0.1 mm (3.973 mil) is placed directly in the center of the device. this via can be used to trace out the center pin connection through another board layer, or it can be left out of the layout 11.2 layout example figure 10. trace example figure 11. example layout with dpw (x2son-5) package solder mask opening, typ metal under solder mask, typ 8 mil 4 mil 8 mil 0402 0.1 ? f bypass capacitor 8 mil worst better best
17 sn74aup1g17 www.ti.com sces579j ? june 2004 ? revised september 2017 product folder links: sn74aup1g17 submit documentation feedback copyright ? 2004 ? 2017, texas instruments incorporated 12 device and documentation support 12.1 documentation support 12.1.1 related documentation for related documentation see the following: ? designing and manufacturing with ti ' s x2son packages ? implications of slow or floating cmos inputs ? how to select little logic ? introduction to logic ? semiconductor packing material electrostatic discharge (esd) protection 12.2 receiving notification of documentation updates to receive notification of documentation updates, navigate to the device product folder on ti.com. in the upper right corner, click on alert me to register and receive a weekly digest of any product information that has changed. for change details, review the revision history included in any revised document. 12.3 community resources the following links connect to ti community resources. linked contents are provided "as is" by the respective contributors. they do not constitute ti specifications and do not necessarily reflect ti's views; see ti's terms of use . ti e2e ? online community ti's engineer-to-engineer (e2e) community. created to foster collaboration among engineers. at e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. design support ti's design support quickly find helpful e2e forums along with design support tools and contact information for technical support. 12.4 trademarks nanostar, e2e are trademarks of texas instruments. all other trademarks are the property of their respective owners. 12.5 electrostatic discharge caution this integrated circuit can be damaged by esd. texas instruments recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper handling and installation procedures can cause damage. esd damage can range from subtle performance degradation to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 12.6 glossary slyz022 ? ti glossary . this glossary lists and explains terms, acronyms, and definitions. 13 mechanical, packaging, and orderable information the following pages include mechanical, packaging, and orderable information. this information is the most current data available for the designated devices. this data is subject to change without notice and revision of this document. for browser-based versions of this data sheet, refer to the left-hand navigation.
package option addendum www.ti.com 12-oct-2017 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples psn74aup1g17dpwr active x2son dpw 5 3000 tbd call ti call ti -40 to 85 sn74aup1g17dbvr active sot-23 dbv 5 3000 green (rohs & no sb/br) cu nipdau | cu sn level-1-260c-unlim -40 to 85 (h175, h17f, h17k, h17r) sn74aup1g17dbvre4 active sot-23 dbv 5 3000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 85 h17f sn74aup1g17dbvrg4 active sot-23 dbv 5 3000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 85 h17f sn74aup1g17dbvt active sot-23 dbv 5 250 green (rohs & no sb/br) cu nipdau | cu sn level-1-260c-unlim -40 to 85 (h175, h17f, h17k, h17r) sn74aup1g17dckr active sc70 dck 5 3000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 85 (h75, h7f, h7k, h7 r) sn74aup1g17dckre4 active sc70 dck 5 3000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 85 (h75, h7f, h7k, h7 r) sn74aup1g17dckrg4 active sc70 dck 5 3000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 85 (h75, h7f, h7k, h7 r) sn74aup1g17dckt active sc70 dck 5 250 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 85 (h75, h7f, h7k, h7 r) sn74aup1g17dcktg4 active sc70 dck 5 250 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 85 (h75, h7f, h7k, h7 r) sn74aup1g17dpwr preview x2son dpw 5 3000 tbd call ti call ti -40 to 85 sn74aup1g17drlr active sot-5x3 drl 5 4000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 85 (h77, h7r) sn74aup1g17dryr active son dry 6 5000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 85 h7 sn74aup1g17dsfr active son dsf 6 5000 green (rohs & no sb/br) cu nipdau | cu nipdauag level-1-260c-unlim -40 to 85 h7 sn74aup1g17yfpr active dsbga yfp 4 3000 green (rohs & no sb/br) snagcu level-1-260c-unlim h7 (2, n) SN74AUP1G17YZPr active dsbga yzp 5 3000 green (rohs & no sb/br) snagcu level-1-260c-unlim -40 to 85 h7n (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect.
package option addendum www.ti.com 12-oct-2017 addendum-page 2 nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) rohs: ti defines "rohs" to mean semiconductor products that are compliant with the current eu rohs requirements for all 10 rohs substances, including the requirement that rohs substance do not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, "rohs" products are suitable for use in specified lead-free processes. ti may reference these types of products as "pb-free". rohs exempt: ti defines "rohs exempt" to mean products that contain lead but are compliant with eu rohs pursuant to a specific eu rohs exemption. green: ti defines "green" to mean the content of chlorine (cl) and bromine (br) based flame retardants meet js709b low halogen requirements of <=1000ppm threshold. antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. other qualified versions of sn74aup1g17 : ? enhanced product: sn74aup1g17-ep note: qualified version definitions: ? enhanced product - supports defense, aerospace and medical applications
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant sn74aup1g17dbvr sot-23 dbv 5 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 q3 sn74aup1g17dbvr sot-23 dbv 5 3000 180.0 8.4 3.23 3.17 1.37 4.0 8.0 q3 sn74aup1g17dbvrg4 sot-23 dbv 5 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 q3 sn74aup1g17dbvt sot-23 dbv 5 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 q3 sn74aup1g17dckr sc70 dck 5 3000 178.0 9.0 2.4 2.5 1.2 4.0 8.0 q3 sn74aup1g17dckr sc70 dck 5 3000 180.0 9.2 2.3 2.55 1.2 4.0 8.0 q3 sn74aup1g17dckr sc70 dck 5 3000 178.0 9.2 2.4 2.4 1.22 4.0 8.0 q3 sn74aup1g17dckr sc70 dck 5 3000 180.0 8.4 2.47 2.3 1.25 4.0 8.0 q3 sn74aup1g17dckt sc70 dck 5 250 178.0 9.0 2.4 2.5 1.2 4.0 8.0 q3 sn74aup1g17dckt sc70 dck 5 250 178.0 9.2 2.4 2.4 1.22 4.0 8.0 q3 sn74aup1g17dckt sc70 dck 5 250 180.0 9.2 2.3 2.55 1.2 4.0 8.0 q3 sn74aup1g17drlr sot-5x3 drl 5 4000 180.0 9.5 1.78 1.78 0.69 4.0 8.0 q3 sn74aup1g17drlr sot-5x3 drl 5 4000 180.0 8.4 1.98 1.78 0.69 4.0 8.0 q3 sn74aup1g17dryr son dry 6 5000 180.0 9.5 1.15 1.6 0.75 4.0 8.0 q1 sn74aup1g17dsfr son dsf 6 5000 180.0 9.5 1.16 1.16 0.5 4.0 8.0 q2 sn74aup1g17yfpr dsbga yfp 4 3000 178.0 9.2 0.89 0.89 0.58 4.0 8.0 q1 SN74AUP1G17YZPr dsbga yzp 5 3000 178.0 9.2 1.02 1.52 0.63 4.0 8.0 q1 package materials information www.ti.com 27-sep-2017 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) sn74aup1g17dbvr sot-23 dbv 5 3000 180.0 180.0 18.0 sn74aup1g17dbvr sot-23 dbv 5 3000 202.0 201.0 28.0 sn74aup1g17dbvrg4 sot-23 dbv 5 3000 180.0 180.0 18.0 sn74aup1g17dbvt sot-23 dbv 5 250 180.0 180.0 18.0 sn74aup1g17dckr sc70 dck 5 3000 180.0 180.0 18.0 sn74aup1g17dckr sc70 dck 5 3000 205.0 200.0 33.0 sn74aup1g17dckr sc70 dck 5 3000 180.0 180.0 18.0 sn74aup1g17dckr sc70 dck 5 3000 202.0 201.0 28.0 sn74aup1g17dckt sc70 dck 5 250 180.0 180.0 18.0 sn74aup1g17dckt sc70 dck 5 250 180.0 180.0 18.0 sn74aup1g17dckt sc70 dck 5 250 205.0 200.0 33.0 sn74aup1g17drlr sot-5x3 drl 5 4000 184.0 184.0 19.0 sn74aup1g17drlr sot-5x3 drl 5 4000 202.0 201.0 28.0 sn74aup1g17dryr son dry 6 5000 184.0 184.0 19.0 sn74aup1g17dsfr son dsf 6 5000 184.0 184.0 19.0 sn74aup1g17yfpr dsbga yfp 4 3000 220.0 220.0 35.0 SN74AUP1G17YZPr dsbga yzp 5 3000 220.0 220.0 35.0 package materials information www.ti.com 27-sep-2017 pack materials-page 2

www.ti.com package outline c 0.5 max 0.19 0.15 1 typ 0.5 typ 5x 0.25 0.21 0.5 typ b e a d 4219492/a 05/2017 dsbga - 0.5 mm max height yzp0005 die size ball grid array notes: 1. all linear dimensions are in millimeters. any dimensions in parenthesis are for reference only. dimensioning and tolerancing per asme y14.5m. 2. this drawing is subject to change without notice. ball a1 corner seating plane ball typ 0.05 c b 1 2 0.015 c a b symm symm c a scale 8.000d: max = e: max = 1.418 mm, min = 0.918 mm, min = 1.358 mm0.858 mm
www.ti.com example board layout 5x ( 0.23) (0.5) typ (0.5) typ ( 0.23) metal 0.05 max ( 0.23) solder mask opening 0.05 min 4219492/a 05/2017 dsbga - 0.5 mm max height yzp0005 die size ball grid array notes: (continued) 3. final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. for more information, see texas instruments literature number snva009 (www.ti.com/lit/snva009). symm symm land pattern example scale:40x 1 2 a b c non-solder mask defined (preferred) solder mask details not to scale solder mask opening solder mask defined metal under solder mask
www.ti.com example stencil design (0.5) typ (0.5) typ 5x ( 0.25) (r0.05) typ metal typ 4219492/a 05/2017 dsbga - 0.5 mm max height yzp0005 die size ball grid array notes: (continued) 4. laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. symm symm solder paste example based on 0.1 mm thick stencil scale:40x 1 2 a b c
www.ti.com package outline c 0.5 max 0.19 0.13 0.4 typ 0.4 typ 4x 0.25 0.21 b e a d 4223507/a 01/2017 dsbga - 0.5 mm max height yfp0004 die size ball grid array notes: 1. all linear dimensions are in millimeters. any dimensions in parenthesis are for reference only. dimensioning and tolerancing per asme y14.5m. 2. this drawing is subject to change without notice. ball a1 corner seating plane ball typ 0.05 c a b 2 0.015 c a b symm symm 1 scale 10.000d: max = e: max = 0.79 mm, min = 0.79 mm, min = 0.73 mm0.73 mm
www.ti.com example board layout 4x ( 0.23) (0.4) typ (0.4) typ ( 0.23) metal 0.05 max solder mask opening metal under solder mask ( 0.23) solder mask opening 0.05 min 4223507/a 01/2017 dsbga - 0.5 mm max height yfp0004 die size ball grid array notes: (continued) 3. final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. for more information, see texas instruments literature number snva009 (www.ti.com/lit/snva009). solder mask details not to scale symm symm land pattern example exposed metal shown scale:50x a b 1 2 non-solder mask defined (preferred) exposed metal solder mask defined exposed metal
www.ti.com example stencil design (0.4) typ (0.4) typ 4x ( 0.25) (r0.05) typ metal typ 4223507/a 01/2017 dsbga - 0.5 mm max height yfp0004 die size ball grid array notes: (continued) 4. laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. symm symm solder paste example based on 0.1 mm thick stencil scale:50x a b 1 2

www.ti.com c 6x 0.22 0.12 6x 0.45 0.35 2x 0.7 4x 0.35 0.4 max 0.05 0.00 a 1.05 0.95 b 1.05 0.95 (0.11) typ (0.1) pin 1 id 4208186/f 10/2014 pin 1 index area seating plane 0.05 c 1 3 4 6 0.07 c a b 0.05 c symm symm notes: 1. all linear dimensions are in millimeters. any dimensions in parenthesis are for reference only. dimensioning and tolerancing per asme y14.5m. 2. this drawing is subject to change without notice. 3. reference jedec registration mo-287, variation x2aaf. mechanical data dsf (s-px2son-n6) plastic small outline no-lead

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